Renesas Electronics: Senior Principal Design Verification Engineer — Chandler, AZ, United States

About Renesas Electronics

Renesas Electronics develops semiconductors for automotive, industrial, infrastructure and connected-device applications. Its employer description identifies microcontrollers, system-on-chip devices, analogue components and power products within its portfolio. These components form part of electronic systems made by other manufacturers. Renesas also describes combining complementary products into solutions for customers, connecting individual chips with the needs of an end application. Its business therefore involves both semiconductor technology and how that technology is used in wider electronic products.

The position and its setting

Renesas Electronics lists Senior Principal Design Verification Engineer in Chandler, AZ, United States, under reference 20032030_2026-08-19. The details below separate the work described by the employer from essential conditions, preferred experience and practical preparation advice.

• Employment type: Full-time
• Employer listing date: 22 October 2026
• Brands: Renesas Electronics

Responsibilities and work described

• Position Overview
• Renesas is seeking an experienced Principal Verification Engineer to lead the verification efforts for our Automotive PMIC (Power Management Integrated Circuit) product line
• This role combines deep expertise in mixed-signal verification methodology with leadership capabilities to mentor junior engineers and drive verification strategy across multiple product platforms
• The ideal candidate will have comprehensive knowledge of analog, digital, and mixed-signal verification techniques, combined with hands-on experience debugging complex automotive power management systems
• Design: and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration for PMIC designs
• Development: and implement comprehensive verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards (ISO 26262, AEC-Q200)
• Set up and optimize Gate-Level Simulation (GLS) flows, correlating with RTL simulation results to identify and resolve discrepancies
• Leadership: debugging activities for complex analog blocks including switched-mode regulators, Linear Dropout (LDO) regulators, and mixed-signal interfaces
• Research / execution: in-depth RTL and Gate-Level simulations, analyzing timing, power, and functional correctness across process, voltage, and temperature (PVT) corners
• Collaboration: closely with cross-functional teams: Design, Application Engineering, ATE (Automatic Test Equipment), and Silicon Validation to ensure seamless verification handoffs
• Mentor and lead junior verification engineers, defining best practices and establishing verification methodologies
• Troubleshoot and debug complex design issues involving interactions between analog and digital domains using simulation and measurement techniques
• Drive continuous improvement of verification tools, methodologies, and infrastructure, evaluating emerging verification technologies and AI-based solutions
• Create and maintain comprehensive verification documentation, test plans, and coverage

Essential requirements and candidate background

• MS or PhD in Electrical Engineering, Computer Engineering, or related
• 12+ years of experience in mixed-signal or analog circuit verification
• Deep understanding of all aspects of mixed-signal verification environment architecture and implementation
• Experience: Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration
• Proficiency: RTL and behavioral simulation tools (e.g., Spectre, Xcelium)
• Understanding: Gate-Level Simulation (GLS) flows and ability to set up and debug GLS simulations
• Expertise debugging both analog blocks (switched-mode regulators, LDO, bandgap, reference circuits) and digital RTL
• Experience: automotive PMIC or power management IC design and verification
• Proficiency: Verilog, SystemVerilog, and/or SPICE-based languages
• Understanding: verification methodologies: UVM, assertions, coverage-driven verification
• Experience interfacing with multiple verification domains: functional, post-silicon, ATE test correlation
• Problem-solving and debugging skills with analytical mindset
• Leadership and mentoring experienc

Location, schedule and contract conditions

For this overseas or regional listing, confirm work authorisation and any location restrictions with the employer. The location does not establish visa sponsorship or permission to work remotely from India.

• Work arrangement: Hybrid
• Advertised location: Chandler, AZ, United States

Pay and application dates

A verified salary figure is not established in this article. An online estimate for another Senior Principal Design Verification Engineer vacancy is not an offer for reference 20032030_2026-08-19; use the employer’s own pay disclosure and recruitment communication.

A closing date is not confirmed in this article. Check the current employer page before submitting: an undated posting can change or be withdrawn.

How to apply to Renesas Electronics

Applications follow the official employer page linked below.

Open the official Renesas Electronics posting below and match the title and reference 20032030_2026-08-19.

Compare your qualifications and experience with the essential conditions for the Chandler, AZ, United States position, then read the preferred criteria separately.

Prepare an accurate CV and the supporting items requested in that employer’s application. Provide only information and documents you are authorised to share.

Use the employer’s application option, complete the required fields and review the submission. Retain the acknowledgement when one is provided. Job Alerts World does not receive the application.

Practical preparation: AI

An AI-related example should make the task and evaluation explicit. Explain the inputs, the system’s intended output and how you checked errors, usefulness or reliability, rather than relying on the model name alone.

Relevant skills

• AI/ML
• ISO
• AI
• compliance
• problem resolution
• electrical engineering