Renesas Electronics: Distinguished Engineer (DE) or Senior Director, Central Engineering – SoC Design & Modeling Methodologies — San Jose, CALIFORNIA, United States

About Renesas Electronics

Renesas Electronics develops semiconductors for automotive, industrial, infrastructure and connected-device applications. Its employer description identifies microcontrollers, system-on-chip devices, analogue components and power products within its portfolio. These components form part of electronic systems made by other manufacturers. Renesas also describes combining complementary products into solutions for customers, connecting individual chips with the needs of an end application. Its business therefore involves both semiconductor technology and how that technology is used in wider electronic products.

The position and its setting

Renesas Electronics lists Distinguished Engineer (DE) or Senior Director, Central Engineering – SoC Design & Modeling Methodologies in San Jose, CALIFORNIA, United States, under reference 20034964_2026-10-16. The details below separate the work described by the employer from essential conditions, preferred experience and practical preparation advice.

• Employment type: Full-time
• Employer listing date: 23 October 2026
• Brands: Renesas Electronics

Responsibilities and work described

• This position will serve as the leader of workload and performance analysis, hardware/software (HW/SW) optimization and co-design (including AI workloads), and SoC architecture
• Expertise in architecture, design, validation, HW/SW optimization, and co-design is required
• Experience in platform design and translating customer-facing requirements into system-level requirements is highly desirable
• The role encompasses workload characterization, solution integration, performance and power tradeoffs, the development of advanced SoC architecture, modeling methodologies, and design enablement strategies across multiple product lines
• The ideal candidate is a recognized technical leader with deep expertise in workload and performance analysis, AI workloads, HW/SW co-design, and SoC architecture
• Technical Leadership
• Define and drive the strategic roadmap for workload analysis and performance for both IPs and products across the company
• Leadership: architecture performance reviews and technical direction for complex IP/SoC and subsystem developments
• Establishment: best practices for hardware/software co-design and model-based development
• Delivery: technical leadership for cross-functional teams spanning architecture, design, verification, emulation, and software
• AI-Driven Engineering Innovation
• Define and analyze AI workloads and the performance required for these workloads
• Organizational Leadership
• Building: and lead high-performing engineering teams
• Mentor directors, principal engineers, and distinguished engineers
• Foster collaboration across Central Engineering, Product Groups, and external partners

Essential requirements and candidate background

• Education
• MS or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline (Ph.D. highly desired)
• 15+ years of experience in semiconductor or SoC development
• 8+ years of technical leadership experience
• Experience leading performance and workload analysis and HW/SW co-optimization
• Understanding of:
• Performance analysis
• Workload analysis
• AI workloads
• SoC architecture and integration
• Digital design methodologies
• IP and subsystem development
• Hardware/software co-design
• SoC verification methodologies
• Hands-on experience with:
• Performance and workload benchmarking
• Virtual platforms and executable specifications
• SoC performance modeling
• Design and verification automation flows

Location, schedule and contract conditions

For this overseas or regional listing, confirm work authorisation and any location restrictions with the employer. The location does not establish visa sponsorship or permission to work remotely from India.

• Work arrangement: On-site
• Advertised location: San Jose, CALIFORNIA, United States

Conditions requiring the complete notice

Some passages contain complex or combined conditions that have not been reduced to short eligibility statements here. Read the complete linked notice for those passages, including any alternatives, exceptions or restrictions. The concise facts above should not be treated as the full wording of every condition.

Pay and application dates

A verified salary figure is not established in this article. An online estimate for another Distinguished Engineer (DE) or Senior Director, Central Engineering – SoC Design & Modeling Methodologies vacancy is not an offer for reference 20034964_2026-10-16; use the employer’s own pay disclosure and recruitment communication.

A closing date is not confirmed in this article. Check the current employer page before submitting: an undated posting can change or be withdrawn.

How to apply to Renesas Electronics

Applications follow the official employer page linked below.

Open the official Renesas Electronics posting below and match the title and reference 20034964_2026-10-16.

Compare your qualifications and experience with the essential conditions for the San Jose, CALIFORNIA, United States position, then read the preferred criteria separately.

Prepare an accurate CV and the supporting items requested in that employer’s application. Provide only information and documents you are authorised to share.

Use the employer’s application option, complete the required fields and review the submission. Retain the acknowledgement when one is provided. Job Alerts World does not receive the application.

Practical preparation: AI

An AI-related example should make the task and evaluation explicit. Explain the inputs, the system’s intended output and how you checked errors, usefulness or reliability, rather than relying on the model name alone.

Relevant skills

• AI/ML
• AI
• electrical engineering